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  • Chip Title: A 11.5-Gbps LDPC Decoder Based on CP-PEG Code Construction
    Desinger : Chih-Lung Chen and Kao-Shou Lin
    Technology : UMC 90nm
    Code Sped : (2048, 1920)
    Code Rate : 0.9375
    Core Area : 3.88mm^2
    Gates : 708K
    Iteration : 4
    Input Quantization : 6 bits
    Clock Frequency : 120 MHz
    Max. Throughput : 11.5 Gbps
    Power : 191.2 mW
    Energy Efficiency : 0.033 nJ/bit
    SNR loss to Shannon limit : 1.6dB
    Feature: 使用實驗室研發的Circulant Permulation Progressive Edge-Growth (CP-PEG) 演算法產生的 (2048, 1920) LDPC Code,具有高編碼率特性以及優秀的解碼效能。硬體架構上採用了Variable-node-centric排程演算法降低疊代(Iteration)以提升解碼速率,並搭配single pipeline架構可節省73%的記憶體使用量。在UMC 90nm CMOS製程實作下能達到11.5Gbps解碼速率,滿足未來高傳輸率的需求。
    Specification: (2048, 1920) CP-PEG LDPC Decoder
    Submission : ESSCIRC2009
    Chip Title: HDC-DCO
    Application: Digitally Controlled Oscillator for SoC integration
    Designer: Man-Chia Chen
    Technology: UMC 90nm CMOS
    Core Area: 60um*20um DCO core with other calibration circuits
    Target Frequency: 3.89MHz-239.2MHz
    Power: 9 μW dynamic @3.89MHz
    Submission: ASSCC2009
    Chip Title: A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit
    Application: Full mode AES-128, AES-192, AES-256
    Designer: Po-Chun Liu
    Technology: UMC 90nm CMOS
    Core Area: 0.044 mm^2
    Throughput: 1.69 Gb/s@131.8MHz
    Power: 5.02mW at 1V, 131.8 MHz
    Submission: ESSCIRC2009
    Chip Title: Soft BCH Decoder for DVB-S2 System
    Application: DVB-S2 System
    Feature: 利用前級LDPC解碼器所提供的軟性資訊來降低後級BCH解碼器的複雜度,使其複雜度為一般BCH解碼器的一半。
    Designer: 林義閔, 陳志龍
    Technology: UMC 90nm CMOS
    Specification: BCH ( 32400, 32208)
    Submission: ASSCC2009
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