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Chip Title: A Frequency Accuracy Enhanced Sub-10μW On-chip Clock Generator Application: Over-Mbps Crystal-less Wireless Biotelemetry System Designer: Wei-Hao Sung, Shu-Yu Hsu, Chien-Ying Yu, Man-Chia Chen Technology: UMC 90nm Core Area: 0.5 x 0.55mm^2 Target Frequency: 5 MHz ± 100ppm Power: 7.6 μW Operation Condition: 1.0V±10% and 0-75°C SNR Requirement: 7dB Submission: Symposium on VLSI Circuits 2010 |
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Chip Title: LINC Signal Component Separator Application: SCS for general OFDM LINC systems Designer: Tsan-Wen Chen, Ping-Yuan Tsai Technology: UMC 90nm CMOS Core Area: 0.2025mm^2 Target Frequency: 50MHz(DSP) / 100MHz(DCPS output) Operation Condition: Voltage 0.5V(DSP) / 1.0V(DCPS) Power: Overall 949.5 μW dynamic Submission: ASSCC2010 |
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Chip Title: A 5.7Gbps Row-Based Layered Scheduling LDPC Decoder for IEEE 802.15.3c Applications Application: 支援IEEE 802.15.3c格規中LDPC Code的四種code-rates Designer: Shiang-Yu Hung, Shao-Wei Yen and Chih-Lung Chen Technology: UMC 65nm CMOS Core area: 1.562mm^2 Frequency: 197MHz Feature: 此晶片完全支援IEEE 802.15.3c通訊標準使用的LDPC Code，採用了row-based layered scheduling來減少疊代次數，此外還使用reconfigurable sorter、sorter input reallocation、pre-coding routing network來降低硬體複雜度。在UMC 65nm CMOS製程下能達到5.76Gbps超越規格的要求，並且低硬體代價與功率消耗都非常具有競爭力。 Specification: (672, 336), (672, 420), (672, 504), (672, 588) LDPC Decoder Submission: ASSCC2010 |
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Chip Title: A 521-bit DF-ECC Processor with Power-Analysis Resistance Designer: Jen-Wei Lee, Yao-Lin Chen Technology: UMC 90nm CMOS Core area: 0.55mm^2 Frequency: 132/166MHz GF(p521)/GF(2^409) Feature: 此晶片支援IEEE P1363雙域橢圓密碼曲線運算，以提出新的Montgomery除法減少運算迴圈，此外使用fully-pipelined和hardware sharing技巧提升硬體效能。在UMC 90nm CMOS製程下能達到19.2/8.2ms GF(p521)/GF(2^409)運算速度，並且還具有simple power-analysis和differential power-analysis抵抗能力。 Specification: 521-bit, dual fields, simple power-analysis and differential power-analysis resistance Submission: ESSCIRC2010 |
NCTU SI2 LAB
System Integration & Silicon Implementation Group