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Chip Title: A Micorpower Biomedical Signal Processor Application: Mobile Healthcare Applications Designer: Shu-Yu Hsu, Po-Yao Chang, Yao-Lin Chen Technology: UMC 90nm Core Area: 900um x 1300um Power: 3pJ/cycle for RISC processing Operation Condition: Voltage 0.5V(Logic)/1.0V(Memory) Submission: A-SSCC2011 |
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Chip Title:A 2.37Gb/s 284.8mW Rate-Compatible (491,3,6) LDPC-CC Decoder Application: 一個具有多碼率的高速低功率低密度同位元迴旋碼解碼器 Designer: 陳志龍, 林玉祥 Technology: UMC 90nm Feature:此解碼器採用(491,3,6) time-varying LDPC-CC Code規格，能夠藉由穿刺技術(puncturing)支援五種code-rates (1/2,2/3,3/4,4/5,5/6)。解碼排程應用了On-demand variable node activation scheduling，能夠提供兩倍的解碼效率，等同於僅需一半的硬體複雜度就可達到原本的錯誤更正能力。此外，更進一步對解碼器架構最佳化，包含1)修改計算過程來隱藏通道值，可減少17%記憶體需求；2) Folding技術，可提高12倍解碼速率；3) Hybrid-partitioned FIFO，在使用記憶體的情況下仍可提供大量頻寬，以應付高速解碼器的頻寬需求，功率消耗也比使用暫存器低。 透過UMC 90nm CMOS製程實作，晶片量測在1.2V電壓下能達到2.37Gb/s解碼速率、功率消耗僅為284.8mW。效能與過去文獻中的LDPC-CC解碼器相比，具有高度競爭力！ Submission: Symposia on VLSI Circuits (SOVC) 2011 |
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Chip Title: LINC Signal Component Separator Application: SCS for OFDM Uneven Multi-Level LINC Systems Designer: Tsan-Wen Chen, Ping-Yuan Tsai Technology: UMC 90nm Core Area: 0.5mm^2 Target Frequency: 40MHz(DSP) / 80MHz(DCPS output) Power: 0.65 mW Operation Condition: Voltage 0.5V(DSP) / 1.0V(DCPS) Submission: ESSCIRC2011 |
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Chip Title: A 2.56 Gb/s Soft RS (255,239) Decoder Chip Application: Optical Communication System Designer: Chih-Hsiang Hsu, Yi-Min Lin Technology: UMC 90nm CMOS Core Area: 216,225 μm2 Target Frequency: 300 MHz Power: 19.6mW Submission: ESSCIRC 2011 |
NCTU SI2 LAB
System Integration & Silicon Implementation Group