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Chip Title: A 1.31Gb/s, 96.6% Utilization Stochastic Nonbinary LDPC Decoder. Application: Small Cells Designer: Xin-Ru Lee, Chih-Wen Yang Technology: UMC 90nm Core Area: 3.75 mm2 Maximum Frequency: 368 MHz Power: 587.7 mW Submission: ESSCIRC 2015 |
NCTU SI2 LAB
System Integration & Silicon Implementation Group