NCTU Course Number

IEE5030

Introductions

This course aims to convey the senior and graudated EE students techniques to design the VLSI chips using state-of-the-art CAD tools. In addition to learning CAD tools for performance-driven and cost-effective IC designs, a top-down design flow and related environment will also be addressed. Upon completion of the course, the student will be able to design the integrated circuits and systems based on standard cell library as well as full-custom layout approaches. As such he/she will be able to work in a team of designers or stand alone.

Important Notice

有意願加簽111學年度第一學期積體電路設計實驗課程的同學
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注意：本學期只開放本校生修習，並且需附上相關課程修課證明
相關課程：
1. 邏輯設計
2. 數位電路與系統
3. 超大型積體電路設計導論(VLSI)/數位積體電路(DIC)

Content

The course starts from system design specs of an application which demands the need of developing specific hardwares or application specific integrated circuits (ASIC) or application processors. Then followed by the presentation of architectural proposals, an optimal architecture leading to performance-driven and cost-effective realization can be derived based on both sampling rate and system clock rate. With the support of Verilog-HDL, designers can describe their designs either in behavioral level or structural level. Before going down to the lower level design, one has to do initial floorplan to estimate both routing style and module aspect ratio which provide some area constraints for later designs. Then the partitioned blocks can be conducted hierarchically and with the support of synthesis as well as P&R routing tools, physical layout can easily be achieved if cell-based design approach is exploited. Finally through layout verification and post-layout simulation, the design can be verified before fabrication.

Reference Book

[1] S. Churiwala and S. Garg,"Principles of VLSI RTL Design" from Springer, ISBN: 978-1-4419-9295-6.
[2] M. Keating, "The Simple Art of SoC Design - Closing the Gap between RTL and ESL" from springer ISBN: 978-1-4419-8585-9.
[3] James M. Lee, "Verilog® Quicstart A Practical Guide to Simulation and Synthesis in Verilog" from Springer, ISBN: 978-0-7923-7672-9.
[4] M.J.S. Smith, "Application-Specific Integrated Circuits," from University of Hawaii, Addison-Wesley, 1997, ISBN 0-201-50022-1. This book covers a lot of design issues and related CAD tools which may interest readers and provide many details for reference.
[5] N.H. Weste and K. Eshraghian, "Principles of CMOS VLSI Design -- A Systems Perspective," 2nd Edition from Addison-Wesley Publishing Company, ISBN 0-201-53376-6.

Instructor

Prof. Chen-Yi Lee 李鎮宜(Office: ED538, Ext: 31849)

TA

Question or Help Requirement on Labs

If there is any question for Labs, please find the help by sending Email to TAs or posting on the FB and NCTU e-campus.

Classroom

The leture is held at ED415.

Grading Criterion

Course Schedule