NCTU Course Number

IEE5030

Introductions

This course aims to convey the senior and graudated EE students techniques to design the VLSI chips using state-of-the-art CAD tools. In addition to learning CAD tools for performance-driven and cost-effective IC designs, a top-down design flow and related environment will also be addressed. Upon completion of the course, the student will be able to design the integrated circuits and systems based on standard cell library as well as full-custom layout approaches. As such he/she will be able to work in a team of designers or stand alone.

Important Notice

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- 2023/ 02 / 03 update Important announcement -

Dear students:
We have decided to allow additional student registration in our course during the first stage registration process.
The following link contains a list of students who were selected through a random selection process and successfully enrolled in the course.
These students submitted their registration forms before the deadline for the first stage registration.
各位同學好，經過衡量教學的量能後，我們決定抽出更多同學加入選課。
以下列表為額外選課成功的同學(該列表的學生是從第一階段填寫截止前的同學中抽出來的)
額外1st選課結果名單:
https://docs.google.com/document/d/1htpSTI-dDvuQLXkGC9WO4H1btTZKllE4TxgyV-wjjWA/edit


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- 2023/ 01 / 16 update Important announcement: 1st registration result:-

The following link is a list of students who have been successfully selected for this course through a random selection process. Please check the online course registration system for confirmation on 1/18 (Wed). Students who filled out the form but were not successful in getting into the course will automatically be included in the second round of random selection and do not need to fill out the form again. Students who have not yet filled out the form and wish to participate in the second round of random selection, please fill out the form in the provided link. If you wish to withdraw your registration form, please send an e-mail and contact TA. For the second stage of registration, there will be more students accepted before 2/20. We will send out e-mails to those who have been accepted and update it on this website. We will accept students that have completed the google form before 2/17 23:59.
以下連結為成功抽籤選上這堂課程的學生列表，請下列學生1/18 (Wed)至選課系統查詢確認。
填寫表單但並未成功選上課程的學生，會自動加入第二次選課的抽籤，無須重複填寫表單。
若尚未填寫表單並希望參與第二次選課的同學，請填寫超連結中的表單。
如果已經填寫表單的同學希望能收回第二階段的申請，請來信聯絡助教。

第二階段選課
表單填寫期限: 2/17 23:59
預計公告時間: 2/20 以電子郵件通知加簽成功同學，名單也會一併公告在實驗室課程網頁
ICLab TA Hsi-Hao Huang
e-mail: hobert0822.ee07@nycu.edu.tw

1st選課結果名單:
https://docs.google.com/document/d/1tm2Yvn8PY7NJzamhCBklJ8QxIORHS0iJkkPx7EGX7lg/edit

2nd選課表單
https://docs.google.com/forms/d/e/1FAIpQLSfIUxnwVFy7V9sjWhysSxTZDL3rJHYMZiXPFSz2saj4mI4QWQ/viewform

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In order to improve the teaching quality of next semester's iclab course, we need to make sure that students have taken courses related to IC designs.
Students that are interested in registering in this IC design lab, please fill out the google form below:
https://docs.google.com/forms/d/e/1FAIpQLSfIUxnwVFy7V9sjWhysSxTZDL3rJHYMZiXPFSz2saj4mI4QWQ/viewform

(For students from NYCU, please fill out the form with your NYCU e-mail account.)
(Please fill out the form in order to register in this course, and do not contact TA or the professor via e-mail to ask us to help you register in this course personally.)
You can only fill out this form once without any modification afterwards. Make sure you read through it carefully!
If there are any new information regarding this course, we will update it on our course website:
http://www.si2lab.org/course/iclab2023spring/
(We will update the website as soon as possible, but the link will not be changed.)
We will send an e-mail to students who have been accepted into the class, and the list of students will also be updated on our course website.
For first stage of registration, we will announce the result before 1/16 on our website.
We will accept students that have completed this survey before 1/12 23:59.
For the second stage of registration, there will be more students accepted before 2/20. We will send out e-mails to those who have been accepted and update it on the website.
We will accept students that have completed this survey before 2/17 23:59.

Content

The course starts from system design specs of an application which demands the need of developing specific hardwares or application specific integrated circuits (ASIC) or application processors. Then followed by the presentation of architectural proposals, an optimal architecture leading to performance-driven and cost-effective realization can be derived based on both sampling rate and system clock rate. With the support of Verilog-HDL, designers can describe their designs either in behavioral level or structural level. Before going down to the lower level design, one has to do initial floorplan to estimate both routing style and module aspect ratio which provide some area constraints for later designs. Then the partitioned blocks can be conducted hierarchically and with the support of synthesis as well as P&R routing tools, physical layout can easily be achieved if cell-based design approach is exploited. Finally through layout verification and post-layout simulation, the design can be verified before fabrication.

Reference Book

[1] S. Churiwala and S. Garg,"Principles of VLSI RTL Design" from Springer, ISBN: 978-1-4419-9295-6.
[2] M. Keating, "The Simple Art of SoC Design - Closing the Gap between RTL and ESL" from springer ISBN: 978-1-4419-8585-9.
[3] James M. Lee, "Verilog® Quicstart A Practical Guide to Simulation and Synthesis in Verilog" from Springer, ISBN: 978-0-7923-7672-9.
[4] M.J.S. Smith, "Application-Specific Integrated Circuits," from University of Hawaii, Addison-Wesley, 1997, ISBN 0-201-50022-1. This book covers a lot of design issues and related CAD tools which may interest readers and provide many details for reference.
[5] N.H. Weste and K. Eshraghian, "Principles of CMOS VLSI Design -- A Systems Perspective," 2nd Edition from Addison-Wesley Publishing Company, ISBN 0-201-53376-6.

Instructor

Prof. Chen-Yi Lee 李鎮宜(Office: ED538, Ext: 31849)

TA

Question or Help Requirement on Labs

If there is any question for Labs, please find the help by sending Email to TAs or posting on the FB and NCTU e-campus.

Classroom

The leture is held at ED415.

Grading Criterion

Course Schedule