Important announcement
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2023/09/12 更新加簽名單:
https://docs.google.com/document/d/1oJ39gXTmRoe32U9Vb-Noht3d-HZ2cS_h6sMql__7lp4/edit?usp=sharing
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各位同學好，由於希望選修VLSI的同學眾多，而實體授課教室會有座位限制，因此會由助教協助統一進行抽籤。
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* 請同學以NYCU的信箱登入填寫
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最新結果請依據公告更新及信件通知，請勿反覆寄信、打擾老師或助教！
請注意：並非填寫表單完成即加簽成功，需經由統一抽籤才能加簽！
請注意：並非填寫表單完成即加簽成功，需經由統一抽籤才能加簽！
請注意：並非填寫表單完成即加簽成功，需經由統一抽籤才能加簽！
Introductions
This course aims to convey junior EE students techniques to analyze and design system by means of VLSI technology and CAD tools. Starting from VLSI process technology and transistor's behavior, an in-depth discussion covering circuit, logic, and subsystem designs will be presented. Upon completion of the course, the student will be able to design system-level IC (SLIC) based on available VLSI technology and CAD tools. As such he/she will be able to work in a team of designers or stand alone to meet system-level specifications.
Content
The course offers a complete yet accessible introduction to crosstalk models and optimization. It covers minimizing power consumption at every level of abstraction, from circuits to architecture and new insights into design-for-testability (DFT) techniques that maximize quality despite quicker turnarounds. It also presents detailed coverage of the algorithms underlying contemporary VLSI computer-aided design (CAD) software, so designers can understand their tools no matter which ones they choose. This course mainly contains 4 topics which are essential to the practice of VLSI design as a system design discipline. They are given below and will be addressed in more detail during lecture and discussion.
Course Material
The text book: "CMOS VLSI Design—A circuits and systems Perspective" by Neil H.E. Weste and David Harris. (2005 3rd Edition)(2010 4th edition)
Lecture Notes (Adapted from the lecture materials by Prof. David Harris)
| Topic 1 | Sep. 13 | Course Outline |
| Course Introduction | ||
| LAB Introduction | ||
| Topic 2 | Sep. 16 | VLSI Introduction |
| Introduction to VLSI Design | ||
| Topic 3 | Sep. 20, 23, 27 | CMOS Transistors and Behaviors 1 |
| Circuits & Layout | ||
| CMOS Transistor Theory | ||
| Topic 4 | Sep. 30 Oct. 4 | CMOS Transistors and Behaviors 2 |
| DC & Transient Response | ||
| Topic 5 | Oct. 7, 11, 14 | Logic Effort and Interconnects |
| Logical Effort | ||
| Interconnects | ||
| Topic 6 | Oct. 18, 21, 25 | Logic gates and families |
| Combinational Circuits | ||
| Circuit Families | ||
| Topic 7 | Oct. 28, Nov. 1 | Sequential Circuits |
| Sequential Circuits | ||
| Topic 8 | Nov. 4, 8 | Adders |
| Adders | ||
| Break for Lab and Exam | Nov. 11, 15 | Mid-Term Exam |
| Topic 9 | Nov. 28, 22 | Data Path and Other Arithmetic Operators |
| Datapath & Arithmetic Operators | ||
| Topic 10 | Nov. 25, 39, Dec 2, 6 | Storage modules and Array structures-1 |
| Random Access Memory | ||
| CAMs, ROMs and PLAs | ||
| Topic 11 | Dec. 6, 9 | Design for Testability |
| Design for Testability | ||
| Topic 12 | Dec. 13, 16 | Design for Package, Power, and IO |
| Package, Power, and IO | ||
| Topic 13 | Dec. 27, 30 | Design for Low Power and Skew |
| Design for Low Power | ||
| Design for Skew | ||
| Break for Lab and Exam | Jan. 3, 6, 10 | Final-Term Exam |
Lab Notes
| Note 1 | Sep. 14 | ED415 Rules |
| ED415 Rules & Introductions | ||
| Note 2 | Sep. 23 | Lab Notes |
| Developing Environment | ||
| Lab_rule | ||
| Note 3 | Sep. 23 | Lab01:Hspice |
| Introduction of Hspice & Ultrasim Simulator | ||
| Exercise: A CMOS Inverter Simulation | ||
| Note 4 | Oct. 11 | Lab02:Hspice |
| Exercise: 1-bit Full Adder Design | ||
| Note 5 | Oct. 18 | Lab03:Layout |
| Introduction to Layout | ||
| Lab3_Example | ||
| Note 6 | Oct. 28 | Lab03:Layout |
| Lab3: 1-Bit Full Adder: Standard Cell Layout | ||
| Note 7 | Nov. 11 | Midterm Proj:Layout |
| Midterm Proj: 8-Bit Full Adder | ||
| Note 8 | Dec. 6 | Lab04:Verilog |
| Lab4: MAC with Four-Mode | ||
| Lab4: Multiplier | ||
| Lab4: Verilog | ||
| Note 9 | Dec. 6 | Final Proj |
| FinalProject: MAC with Four-Mode |
Lab Video
| Video 1 | Sep. 20 | HSPICE Training Course |
| Lab01 Training Course Video | ||
| Video 2 | Sep. 20 | Solaris OS & Cadence Composer Training Course |
| Lab02-1 Training Course Video | ||
| Video 3 | Sep. 20 | Virtuoso/ Laker Layout & Design Check Training Course |
| Lab02-2 Training Course Video | ||
| Video 4 | Sep. 20 | Calibre LPE & Post-Simulation |
| Lab02-3 Training Course Video |
Past-year questions
Instructor
Chen-Yi Lee 李鎮宜(Office: ED538, ext: 31849, E-mail: cylee@faculty.nctu.edu.tw)
Office Hour: Every Wen from 10:00 to 12:00.
TA
| VLSI TA | 謝承軒 | frank8771919.ee11@nycu.edu.tw | Ext.54238 |
Office hour of TA : Every Thur. from 18:30 to 20:30 at ED430
Welcome for any special Events by e-mail or phone .