[167] Eugene Lee, Cheng-Han Huang, Chen-Yi Lee " Few-Shot and Continual Learning with Attentive Independent Mechanisms,," In Proceedings of the International Conference of Computer Vision (ICCV) 2021.

[166] Eugene Lee, Annie Ho, Yi-Ting Wang, Cheng-Han Huang, Chen-Yi Lee " Cross-Domain Adaptation for Biometric Identification Using Photoplethysmogram,," International Conference on Acoustics, Speech, and Signal Processing (ICASSP) 2020.

[165] Eugene Lee and Chen-Yi Lee " NeuralScale: Efficient Scaling of Neurons in Resource-Constrained Deep Neural Networks (oral),," In Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition (CVPR) 2020.

[164] Eugene Lee, Evan Chen and Chen-Yi Lee " Meta-rPPG: Remote Heart Rate Estimation Using a Transductive Meta-Learner,," In Proceedings of the European Conference of Computer Vision (ECCV)2020.

[163] Lee, Eugene, Tsu-Jui Hsu, and Chen-Yi Lee National Chiao Tung University, Taiwan "Centralized State Sensing using Sensor Array on Wearable Device,," IEEE International Symposium on Circuits and Systems (ISCAS) 2019.

[162] Yi-Wei Chen, National Chiao Tung University, Taiwan; Tung-Yu Wu, Wing-Hung Wong, Stanford University, United States; Chen-Yi Lee, National Chiao Tung University, Taiwan "DIABETIC RETINOPATHY DETECTION BASED ON DEEP CONVOLUTIONAL NEURAL NETWORKS,," IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) 2018.

[161] Heng-Wei Hsu, National Chiao Tung University, Taiwan; Tung-Yu Wu, Wing-Hung Wong, Stanford University, United States; Chen-Yi Lee, National Chiao Tung University, Taiwan "CORRELATION-BASED FACE DETECTION FOR RECOGNIZING FACES IN VIDEOS,," IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) 2018.

[160] Sheng Wan, National Chiao Tung University, Taiwan; Tung-Yu Wu, Wing-Hung Wong, Stanford University, United States; Chen-Yi Lee, National Chiao Tung University, Taiwan "CONFNET: PREDICT WITH CONFIDENCE,," IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) 2018.

[159] Cheng-Hsiang Cheng, Ping-Yuan Tsai, Tzu-Yi Yang, Wan-Hsueh Cheng, Ting-Yang Yen, Zhicong Luo, Xin-Hong Qian, Zhi-Xin Chen, Tsu-Han Lin, Wei-Hong Chen, Wei-Ming Chen, Sheng-Fu Liang, Fu-Zen Shaw, Cheng-Siu Chang, Fu-Yuan Shih ,Yue-Loong Hsin, Chen-Yi Lee, Ming-Dou Ker, and Chung-Yu Wu,"A Fully Integrated Closed-Loop Neuromodulation SoC with Wireless Power and Bi-directional Data Telemetry for Real-Time Human Epileptic Seizure Control,," IEEE Symposium on VLSI Circuits, Aug. 2017

[158] Chung-Yu Wu, Cheng-Hsiang Cheng, Yi-Huan Ou-Yang, Chiung-Chu Chen, Wei-Ming Chen, Ming-Dou Ker, Chen-Yi Lee, Sheng-Fu Liang, Fu-Zen Shaw "Design considerations and clinical applications of closed-loop neural disorder control SoCs," IEEE Design Automation Conference (ASP-DAC), 2017 22nd Asia and South Pacific.

[157] Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, and Chen-Yi Lee, "A 1.31Gb/s, 96.6% Utilization Stochastic Nonbinary LDPC Decoder for Small Cell Applications,," IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 96-99, Sep. 2015.

[156] Ping-Yuan Tsai, Yu-Yun Chang, Shu-Yu Hsu, Chen-Yi Lee, "An OFDM-based 29.1Mbps 0.22nJ/bit body channel communication baseband transceiver," VLSI-DAT 2015: 1-4.

[155] Chang-Hung Tsai, Hui-Hsuan Lee, Wan-Ju Yu, Chen-Yi Lee: "A 2 GOPS quad-mean shift processor with early termination for machine learning applications,," ISCAS 2014: 157-160

[154] Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, and Chen-Yi Lee, "A 1.31Gb/s, 96.6% Utilization Stochastic Nonbinary LDPC Decoder for Small Cell Applications,," IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 96-99, Sep. 2015. (pdf)

[153] Kelvin Yi-Tse Lai, Yu-Tao Yang, Bang-Jing Chen, Chun-Jen Shen, Ming-Feng Shiu, Zih-Cheng He, Hsie-Chia Chang, and Chen-Yi Lee, "A 3.3V 15.6b 6.1pJ/0.02%RH with 10ms Response Humidity Sensor for Respiratory Monitoring," IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2014, pp. 293-296.

[152] Chen-Yi Lee, Kelvin Yi-Tse Lai, and Shu-Yu Hsu, "Event-Driven Read-Out Circuits for Eenergy-Efficient Sensor-SoC’s," IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) (invited), Apr. 2014, pp.1-2.

[151] Chih-Lung Chen, Sheng-Jhan Wu, Hsie-Chia Chang, and Chen-Yi Lee, "A 1‐100Mb/S 0.5‐9.9mW LDPC Convolutional Code Decoder for Body Area Network,," IEEE Asian Solid-State Circuits Conference (ASSCC), pp. 229-232, Nov. 2014. (pdf)

[150] Chih-Wen Yang, Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, and Chen-Yi Lee, "Area-efficient TFM-based Stochastic Decoder Design for Non-binary LDPC Codes," IEEE International Symposium on Circuits and Systems (ISCAS), June 2014, pp. 409-412. (pdf)

[149] Chih-Lung Chen, Yu-Cheng Lan, Hsie-Chia Chang, and Chen-Yi Lee, "A 3.66Gb/s 275mW TB-LDPC-CC Decoder Chip for MIMO Broadcasting Communications," IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2013, pp. 153-156. (pdf)

[148] Chang-Hung Tsai, Hsiuan-Ting Wang, Chia-Lin Liu, Yao Li, Chen-Yi Lee, "A 446.6K-Gates 0.55-1.2V H.265/HEVC Decoder for Next Generation Video Applications," IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2013.

[147] Kelvin Yi-Tse Lai, Zih-Cheng He, Yu-Tao Yang, Hsie-Chia Chang, Chen-Yi Lee, "A 0.0354mm2 82uW 125KS/s 3-Axis Readout Circuit for Capacitive MEMS Accelerometer," IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2013.

[146] Kelvin Yi-Tse Lai, Yu-Tao Yang, Gary Wang, Yi-Wen Lu, and Chen-Yi Lee, "A DIGITAL MICROFLUIDIC PROCESSOR FOR BIOMEDICAL APPLICATIONS," IEEE Workshop on Signal Processing System (SIPS), Oct. 2013.

[145] Shu-Yu Hsu, Yingchieh Ho, Po-Yao Chang, Pei-Yu Hsu, Chien-Ying Yu, Yuhwai Tseng, Tze-Zheng Yang, Ten-Fang Yang, Ray-Jade Chen, Chauchin Su, Chen-Yi Lee, " A 48.6-to-105.2μW Machine-Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Monitoring," IEEE Symposium on VLSI Circuits (VLSIC), Jun. 2013, pp. 252-253.

[144] Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, and Chen-Yi Lee, "A 3.40ms/GF(p_521) and 2.77ms/GF(2^521) DF-ECC Processor with Side-Channel Attack Resistance," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2013.

[143] Po-Yao Chang, Shu-Yu Hsu, Chen-Yi Lee, "A 4.88μW ECG Delineator Using Wavelet Transform for Mobile Healthcare Application," IEEE Biomedical Circuits and Systems Conference (BioCAS), pp. 376-379, Nov. 2012.

[142] Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, and Chen-Yi Lee, "An Efficient Countermeasure Against Correlation Power-Analysis Attacks With Randomized Montgomery Operations for DF-ECC Processor," Cryptographic Hardware and Embedded Systems (CHES'12), vol. 7428, Sep. 2012, pp. 548-564. (pdf)

[141] Shu-Yu Hsu, Ying-Chieh Ho, Yuh-Wai Tseng, Ting-You Lin, Po-Yao Chang, Jen-Wei Lee, Ju-Hung Hsiao, Siou-Ming Chuang, Tze-Zheng Yang, Po-Chun Liu, Ten-Fang Yang, Ray-Jade Chen, Chau-Chin Su, Chen-Yi Lee, "A Sub-100μW Multi-Functional Cardiac Signal Processor for Mobile Healthcare Applications," IEEE Symposium on VLSI Circuits (VLSIC'12), Jun. 2012, pp. 156-157. (pdf)

[140] Ping-Yuan Tsai, Shu-Yu Hsu, Jen-Shin Chang, Tsan-Wen Chen and Chen-Yi Lee, "A QPSK/16-QAM OFDM-Based 29.1Mbps LINC Transmitter for Body Channel Communication," IEEE Asian Solid-State Circuits Conference (ASSCC), Nov.2012.

[139] Chia-Lung Lin, Chih-Lung Chen, Hsie-Chia Chang, and Chen-Yi Lee, "A (50,2,4) Nonbinary LDPC Convolutional Code Decoder Chip over GF(256) in 90nm CMOS", IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2012, pp. 201-204. (pdf)

[138] Szu-Chi Chung, Jen-Wei Lee, Hsie-Chia Chang, and Chen-Yi Lee, "A High-Performance Elliptic Curve Cryptographic Processor Over GF(p) with SPA Resistance," IEEE International Symposium on Circuits and Systems (ISCAS), May 2012, pp. 1456-1459. (pdf)

[137] Yi-Huan Ou-Yang, Chien-Yu Kao, Jen-Yuan Hsu, Pang-An Ting, and Chen-Yi Lee, "Extrinsic Data Compression Method for Double-Binary Turbo Codes," IEEE International Symposium on Circuits and Systems (ISCAS), May 2012, pp. 1775-1778. (pdf)

[136] Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, and Chen-Yi Lee, "Stochastic Decoding for LDPC Convolutional Codes," IEEE International Symposium on Circuits and Systems (ISCAS), May 2012, pp. 2621-2624. (pdf)

[135] Ming-Yu Kuo, Yao Li, and Chen-Yi Lee, "An Area-efficient High-accuracy Prediction-based CABAC Decoder Architecture for H.264/AVC," IEEE International Symposium on Circuits and Systems (ISCAS), May 2012, pp. 1960-1963. (pdf)

[134] Po-Chun Liu, Ju-Hung Hsiao, Hsie-Chia Chang, and Chen-Yi Lee, "A 2.97 Gb/s DPA-Resistant AES Engine with Self-Generated Random Sequence," European Solid-State Circuits Conference (ESSCIRC), pp.71-74, Sep. 2011.

[133] Chih-Lung Chen, Yu-Hsiang Lin, Hsie-Chia Chang, and Chen-Yi Lee, "A 2.37Gb/s 284.8mW Rate-Compatible (491,3,6) LDPC-CC Decoder," IEEE Symposium on VLSI Circuits (VLSIC), Jun. 2011, pp. 134-135. (pdf)

[132] Shu-Yu Hsu, Yao-Lin Chen, Po-Yao Chang, Jui-Yuan Yu, Ten-Fang Yang, Ray-Jade Chen, and Chen-Yi Lee, "A Micropower Biomedical Signal Processor for Mobile Healthcare Applications," IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2011. (pdf)

[131] Chien-Ying Yu and Chen-Yi Lee, "A 0.6V 200kHz Silicon Oscillator with Temperature Compensation for Wireless Sensing Applications," IEEE Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2011. (pdf)

[130] Tsan-Wen Chen, Ping-Yuan Tsai, Jui-Yuan Yu, and Chen-Yi Lee, "A 0.67mW 14.55Mbps OFDM-Based Sensor Node Transmitter for Body Channel Communications," IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2011. (pdf)

[129] Tzu-Chun Shih, Tsan-Wen Chen, Wei-Hao Sung, Ping-Yuan Tasi, and Chen-Yi Lee, "An Energy-Efficient OFDM-Based Baseband Transceiver Design for Ubiquitous Healthcare Monitoring Applications," IEEE Interational System-on-Chip Conference (SOCC), Sep. 2011. (pdf)

[128] Ping-Yuan Tsai, Tsan-Wen Chen, and Chen-Yi Lee, "A Low-Power All-Digital Phase Modulator Pair For LINC Transmitters," IEEE Interational System-on-Chip Conference (SOCC), Sep. 2011. (pdf)

[127] Tsan-Wen Chen, Ping-Yuan Tsai, Dieter De Moitie, Jui-Yuan Yu, and Chen-Yi Lee, "A Low Power All-Digital Signal Component Separator for Uneven Multi-Level LINC Systems," European Solid-State Circuits Conference (ESSCIRC), Sep. 2011, pp. 403-406. (pdf)

[126] Chih-Hsiang Hsu, Yi-Min Lin, Hsie-Chia Chang, and Chen-Yi Lee, "A 2.56 Gb/s Soft RS (255,239) Decoder Chip for Optical Communication Systems," European Solid-State Circuits Conference (ESSCIRC), Sep. 2011, pp. 79-82. (pdf)

[125] Yao-Lin Chen, Jen-Wei Lee, Po-Chun Liu, Hsie-Chia Chang, and Chen-Yi Lee, "A dual-field elliptic curve cryptographic processor with a radix-4 unified division unit," IEEE International Symposium on Circuits and Systems (ISCAS), May. 2011. (pdf)

[124] Shiang-Yu Hung, Shao-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, and Chen-Yi Lee, "A 5.7Gbps Row-Based Layered Scheduling LDPC Decoder for IEEE 802.15.3c Applications," IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2010. (pdf)

[123] Xin-Ru Lee, Hsie-Chia Chang, and Chen-Yi Lee, "A Low-Power Radix-4 Viterbi Decoder Based on DCVSPG Pulsed Latch with Sharing Technique," IEEE Asian Pacific Conference on Circuits and Systems (APCCAS), Dec. 2010, pp. 1203-1206. (pdf)

[122] Tsan-Wen Chen, Ping-Yuan Tsai, Jui-Yuan Yu, and Chen-Yi Lee, "A Sub-mW All-Digital Signal Component Separator with Branch Mismatch Compensation for LINC Transmitters," IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2010, pp. 209-213. (pdf)

[121] Tsan-Wen Chen, Ping-Yuan Tsai, Jui-Yuan Yu, and Chen-Yi Lee, "A Low Power All-Digital Signal Component Separator for OFDM LINC Systems," IEEE International Conference on Green Circuits and Systems (ICGCS), Jun. 2010, pp. 328-333. (pdf)

[120] Jen-Wei Lee, Yao-Lin Chen, Chih-Yeh Tseng, Hsie-Chia Chang, and Chen-Yi Lee, "A 521-bit Dual-Field Elliptic Curve Cryptographic Processor with Power Analysis Resistance," European Solid-State Circuits Conference (ESSCIRC), 2010, pp. 206-209. (pdf)

[119] Yi-Min Lin, Hsie-Chia Chang, and Chen-Yi Lee, "An Improved Soft BCH Decoder with One Extra Error Compensation," IEEE International Symposium on Circuits and Systems (ISCAS), May 2010, pp. 3941-3944. (pdf)

[118] Wei-Hao Sung, Shu-Yu Hsu, Jui-Yuan Yu, Chien-Ying Yu, and Chen-Yi Lee, "A Frequency Accuracy Enhanced Sub-10μW On-chip Clock Generator for Energy Efficient Crystal-less Wireless Biotelemetry Applications," IEEE Symposium on VLSI Circuits (VLSIC), Jun. 2010, pp. 115-116. (pdf)

[117] Hsiao-Han Ma, Chien-Ying Yu, Jui-Yuan Yu, and Chen-Yi Lee, "A Synchronization Method for Crystal-Less OFDM-Based Wireless Body Area Network Applications," IEEE International SoC Conference (ISOCC), Nov. 2009, pp. 448-451. (pdf)

[116] Chih-Lung Chen, Kao-Shou Lin, Hsie-Chia Chang, Wai-Chi Fang, and Chen-Yi Lee, "A 11.5-Gbps LDPC Decoder Based on CP-PEG Code Construction," European Solid-State Circuits Conference (ESSCIRC), 2009. (pdf)

[115] Po-Chun Liu, Hsie-Chia Chang, and Chen-Yi Lee, "A 1.69 Gb/s Area-Efficient AES Crypto Core with Compact On-the-fly Key Expansion Unit," European Solid-State Circuits Conference (ESSCIRC), 2009. (pdf)

[114] Man-Chia Chen, Jui-Yuan Yu, and Chen-Yi Lee, "A Sub-100μW Area-Efficient Digitally-Controlled Oscillator Based on Hysteresis Delay Cell Topologies," IEEE Asian Solid-State Circuits Conference (ASSCC), 2009. (pdf)

[113] Yi-Min Lin, Chih-Lung Chen, Hsie-Chia Chang, and Chen-Yi Lee, "A 26.9K 314.5Mbps Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System," IEEE Asian Solid-State Circuits Conference (ASSCC), 2009. (pdf)

[112] Shao-Wei Yen, Ming-Chih Hu, Chih-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, and Chen-Yi Lee, "A 0.92mm2 23.4mW Fully-Compliant CTC Decoder for WiMAX 802.16e Application," IEEE Custom Integrated Circuits Conference (CICC), 2009, pp.191-194. (pdf)

[111] Chien-Ying Yu, Jui-Yuan Yu, and Chen-Yi Lee, "An eCrystal Oscillator with Self-Calibration Capability," IEEE International Symposium on Circuits and Systems (ISCAS), May 2009. (pdf)

[110] Yu-Fan Lai, Tsu-Ming Liu, Yao Li, and Chen-Yi Lee, "Design of An Intra Predictor with Data Reuse for High-Profile H.264 Applications," IEEE International Symposium on Circuits and Systems (ISCAS), May 2009. (pdf)

[109] Kuan-Ling Kuo, Tsan-Wen Chen, Carrson C. Fung, and Chen-Yi Lee, "Second-Order Statistics Based Prefilter-Blind Equalization for MIMO-OFDM," IEEE Asia-Pacific Conference on Communications (APCC), Oct. 2008. (pdf)

[108] Chih-Hao Liu, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, and Yarsun Hsu, "Multi-mode message passing switch networks applied for QC-LDPC decoder," IEEE International Symposium on Circuits and Systems (ISCAS), 2008, pp. 752-755. (pdf)

[107] Duo Sheng, Ching Che Chung, and Chen Yi Lee, "An all digital spread spectrum clock generator with programmable spread ratio for SoC applications," IEEE Asian Solid-State Circuits Conference (ASSCC), 2008. (pdf)

[106] Jui-Yuan Yu, Chien-Ying Yu, Shang-Bin Huang, Tsan-Wen Chen, Juinn-Ting Chen, Kuan-Ling Kuo, and Chen-Yi Lee, "A 0.5V 4.85Mbps Dual-Mode Baseband Transceiver with Extended Frequency Calibration for Biotelemetry Applications," IEEE Asian Solid-State Circuits Conference (ASSCC), 2008. (pdf)

[105] Yu-De Wu, Yao Li, and Chen-Yi Lee, "A Novel Embedded Bandwidth-Aware Frame Compressor for Mobile Video Applications," IEEE International Workshop on Intelligent Signal Processing and Communication Systems (ISPACS), 2008. (pdf)

[104] Wei-Chin Lee, Yao Li, and Chen-Yi Lee, "Design of A Memory-Based VLC Decoder for Portable Video Applications," IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), 2008. (pdf)

[103] Hsiao-Han Ma, Jui-Yuan Yu, Tsan-Wen Chen, Chien-Ying Yu, and Chen-Yi Lee, "An OFDMA-Based Wireless Body Area Network using Frequency Pre-Calibration," IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT), Apr. 2008, pp. 192-195. (pdf)

[102] Wen-Ping Lee, Tsu-Ming Liu, and Chen-Yi Lee, "A Joint Architecture of Error-Concealed Deblocking Filter for H.264/AVC Video Transmission," IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT), Apr. 2007, pp. 184-187. (pdf)

[101] Mei-Hui Yang, Jui-Yuan Yu, Juinn-Ting Chen, and Chen-Yi Lee, "A Dynamic Phase-Frequency Recovery for Power Reduction in OFDM Systems," IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT), Apr. 2007, pp. 107-110. (pdf)

[100] Terng-Ren Hsu, Terng-Yin Hsu, and Chen-Yi Lee, "Generalized MLP/BP-based MIMO DFEs for Overcoming ISI and ACI in Bandlimited Channels," IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT), Apr. 2007, pp. 103-106. (pdf)

[99] Dah-Jia Lin, Chien-Ching Lin, Chih-Lung Chen, Hsie-Chia Chang, and Chen-Yi Lee, "A LOW-POWER VITERBI DECODER BASED ON SCARCE STATE TRANSITION AND VARIABLE TRUNCATION LENGTH," IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT), Apr. 2007. (pdf)

[98] Jui-Yuan Yu, Ching-Che Chung, Wan-Chun Liao, and Chen-Yi Lee, "A sub-mW Multi-Tone CDMA Baseband Transceiver Chipset for Wireless Body Area Network Applications," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2007. (pdf)

[97] Jui-Yuan Yu, Wan-Chun Liao, and Chen-Yi Lee, "An MT-CDMA Based Wireless Body Area Network for Ubiquitous Healthcare Monitoring," IEEE Biomedical Circuits and Systems Conference (BioCAS), Nov. 2006. (pdf)

[96] Jui-Yuan Yu, Ching-Che Chung, Hsuan-Yu Liu, and Chen-Yi Lee, "Power Reduction with Dynamic Sampling and All-Digital I/Q-Mismatch Calibration for A MB-OFDM UWB Baseband Transceiver," IEEE International Symposium on Low Power Electronics and Design (ISLPED), Oct. 2006. (pdf)

[95] Jui-Yuan Yu, Ching-Che Chung, Hsuan-Yu Liu, Yu-Wei Lin, Wan-Chun Liao, Terng-Yin Hsu, and Chen-Yi Lee, "A 31.2mW UWB Baseband Transceiver with All-Digital I/Q-mismatch Calibration and Dynamic Sampling," IEEE Symposium on VLSI Circuits (VLSIC), Jun. 2006, pp. 290-291. (pdf)

[94] Yuan Chen, Yu-Wei Lin, and Chen-Yi Lee, "A Block Scaling FFT/IFFT Processor for WiMAX Applications," IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2006. (pdf)

[93] Tsu-Ming Liu and Chen-Yi Lee, "An Improved Soft-Input CAVLC Decoder for Mobile Communication Applications," IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), 2006. (pdf)

[92] Shao-Ming Sun, Tsu-Ming Liu, and Chen-Yi Lee, "A Self-Grouping and Table-Merging Algorithm for VLC-Based Video Decoding System," IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), 2006. (pdf)

[91] Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, "A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications," IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), 2006. (pdf)

[90] Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, "An All-Digital Phase-Locked Loop with High-Resolution for SoC Applications," IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT), Apr. 2006. (pdf)

[89] Ching-Che Chung, Pao-Lung, and Chen-Yi Lee, "An All-Digital Delay-Locked Loop for DDR SDRAM Controller Applications," IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT), Apr. 2006. (pdf)

[88] Ying-Hao Ma, Lei-Fone Chen, and Chen-Yi Lee, "A Design of Channel Equalizer for COFDM System," IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT), Apr. 2006. (pdf)

[87] Chen-Yi Lee, "SoC for Wireless COFDM Systems: Challenges and Opportunities (Invited)," IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT), Apr. 2006. (pdf)

[86] Tsu-Ming Liu, and Chen-Yi Lee, "Memory-Hierarchy-Based Power Reduction for H.264/AVC Video Decoder," IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT), Apr. 2006. (pdf)

[85] Tsu-Ming Liu, Ting-An Lin, Sheng-Zen Wang, Wen-Ping Lee, Kang-Cheng Hou, Jiun-Yan Yang, and Chen-Yi Lee, "A 125-μW, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications," IEEE International Solid-State Circuits Conference (ISSCC), 2006, pp. 402-403. (pdf)

[84] L.-F. Chen, Y. Chen, L.-C. Chien, Y.-H. Ma, C.-H. Lee, Y.-W. Lin, C.-C. Lin, H.-Y. Liu, T.-Y. Hsu, and C-Y. Lee, "A 1.8V 250mW COFDM Baseband Receiver for DVB-T/H Applications," IEEE International Solid-State Circuits Conference (ISSCC), 2006. (pdf)

[83] Tsu-Ming Liu, Ching-Che Chung, Chen-Yi Lee, Ting-An Lin, and Sheng-Zen Wang, "Design of a 125μW, Fully-Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications," ACM/IEEE Design Automation Conference, 2006, pp. 288-289. (pdf)

[82] Fuke Chang, Chienching Lin, Hsie-Chia Chang, and Chen-Yi Lee, "A Universal Architecture for RS Error and Erasure Decoder," IEEE Asian Solid-State Circuits Conference (ASSCC), 2005. (pdf)

[81] Yu-Wei Lin, Wan-Chun Liao, and Chen-Yi Lee, "A MRMDF FFT Processor for MIMO OFDM Applications," IEEE Asian Solid-State Circuits Conference (ASSCC), 2005. (pdf)

[80] Tsu-Ming Liu, Ting-An Lin, Sheng-Zen Wang, Wen-Ping Lee, Kang-Cheng Hou, Jiun-Yan Yang, and Chen-Yi Lee, "An 865-μW H.264/AVC Video Decoder for Mobile Applications," IEEE Asian Solid-State Circuits Conference (ASSCC), 2005, pp. 301-304. (pdf)

[79] Sheng-Zen Wang, Ting-An Lin, Tsu-Ming Liu, and Chen-Yi Lee, "A New Motion Compensation Design for H.264/AVC Decoder," IEEE International Symposium on Circuits and Systems (ISCAS), May 2005, pp. 4558-4561. (pdf)

[78] Tsu-Ming Liu, Wen-Ping Lee, Ting-An Lin, and Chen-Yi Lee, "A Memory-Efficient Deblocking Filter for H.264/Avc Video Coding," IEEE International Symposium on Circuits and Systems (ISCAS), May 2005, pp. 2140-2143. (pdf)

[77] Ting-An Lin and Chen-Yi Lee, "Predictive Equalizer Design for Dvb-T System," IEEE International Symposium on Circuits and Systems (ISCAS), May 2005, pp. 940-943. (pdf)

[76] Pao-Lung Chen, Ching-Che Chung, and Chen-Yi Lee, "An All-Digital PLL with Cascaded Dynamic Phase Average Loop for Wide Multiplication Range Applications," IEEE International Symposium on Circuits and Systems (ISCAS), May 2005, pp. 4875-4878. (pdf)

[75] Ting-An Lin, Sheng-Zen Wang, Tsu-Ming Liu, and Chen-Yi Lee, "An H.264/AVC Decoder with 4X4-Block Level Pipeline," IEEE International Symposium on Circuits and Systems (ISCAS), May 2005, pp. 1810-1813. (pdf)

[74] Jui-Yuan Yu, Ming-Fu Sun, Terng-Yin Hsu, and Chen-Yi Lee, "A Novel Technique for I/Q Imbalance and CFO Compensation in OFDM Systems," IEEE International Symposium on Circuits and Systems (ISCAS), May 2005, pp. 6030-6033. (pdf)

[73] Hsuan-Yu Liu, Chien-Ching Lin, Yu-Wei Lin, Ching-Che Chung, Kai-Li Lin, Wei-Che Chang, Lin-Hung Chen, Hsie-Chia Chang, and Chen-Yi Lee, "A 480Mb/s LDPC-COFDM-based UWB baseband transceiver," IEEE International Solid-State Circuits Conference (ISSCC), 2005, pp. 444-446. (pdf)

[72] Wei-Che Chang, Lin-Hung Chen, Wan-Chun Liao, Hsuan-Yu Liu, and Chen-Yi Lee, "An area and power efficient frame synchronizer for 480Mb/s OFDM-based UWB system," IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT), 2005, pp. 84-87. (pdf)

[71] Lin-Hung Chen, Wei-Che Chang, Hsuan-Yu Liu, and Chen-Yi Lee, "A 528MS/s frequency synchronizer for OFDM-based UWB system," IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT), 2005, pp. 88-91. (pdf)

[70] Ting-An Lin, Tsu-Ming Liu, and Chen-Yi Lee, "A low-power H.264/AVC decoder," IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT), 2005, pp. 283-286. (pdf)

[69] Chien-Ching Lin, Kai-Li Lin, Hsie-Chia Chang, and Chen-Yi Lee, "A 3.33gb/s (1200,720) low-density parity check code decoder," European Solid-State Circuits Conference (ESSCIRC), 2005, pp. 211-214. (pdf)

[68] Yuan-Mao Chang, Cheng-Wei Kuang, Chien-Ching Lin, Tzu-Shien Sang, Hsie-Chia Chang, and Chen-Yi Lee, "A new channel equalizer for OFDM-based wireless communications," IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT), 2005, pp. 104-107. (pdf)

[67] Tsu-Ming Liu, Wen-Ping Lee, and Chen-Yi Lee, "An Area-Efficient and High-Throughput De-Blocking Filter for Multi-Standard Video Applications," IEEE International Conference on Image Processing (ICIP), 2005, pp. III-1044-1047. (pdf)

[66] Chien-Ching Lin, Fuh-Ke Chang, Hsie-Chia Chang, and Chen-Yi Lee, "A universal VLSI architecture for bit-parallel computation in GF(2/sup m/)," IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), 2004, vol. 1, pp. 125-128. (pdf)

[65] Tsu-Ming Liu, Sheng-Zen Wang, Wen-Hsiao Peng, and Chen-Yi Lee, "Memory efficient and low complexity scalable soft VLC decoding for the video transmission," IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), 2004, vol. 2, pp. 673-676. (pdf)

[64] Yi-Hsin Yu, Hsuan-Yu Liu, Terng-Yin Hsu, and Chen-Yi Lee, "A joint scheme of decision-directed channel estimation and weighted-average phase error tracking for OFDM WLAN systems," IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), 2004, vol. 2, pp. 985-988. (pdf)

[63] Yu-Wei Lin and Chen-Yi Lee, "A new dynamic scaling FFT processor," IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), 2004, vol. 1, pp. 449-452. (pdf)

[62] Tsu-Ming Liu and Chen-Yi Lee, "A low-complexity soft VLC decoder using performance modeling," IEEE International Conference on Image Processing (ICIP), vol. 5, pp. 3233-3236. (pdf)

[61] Ming-Juei Wu, Jyh-Neng Yang, and Chen-Yi Lee, "A constant power consumption CMOS LC oscillator using improved high-Q active inductor with wide tuning-range," IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), vol. 3, pp. III-347-50. (pdf)

[60] Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, and Chen-Yi Lee, "A dual mode channel decoder for 3GPP2 mobile wireless communications," European Solid-State Circuits Conference (ESSCIRC), Sept. 2004, pp. 483-486. (pdf)

[59] Hsuan-Yu Liu, Yi-Hsin Yu, Chien-Ching Lin, Ching-Che Chung, Terng-Yi Hsu, and Chen-Yi Lee, "A COFDM baseband processor with robust synchronization for high-speed WLAN applications," IEEE Symposium on VLSI Circuits (VLSIC), 2004, pp. 156-159. (pdf)

[58] Cheng-Hung Liu, Bai-Jue Shieh, and Chen-Yi Lee, "A low-power group-based VLD design," IEEE International Symposium on Circuits and Systems (ISCAS), vol. 2, pp. II-337-40. (pdf)

[57] Yi-Chen Tseng, Chien-Ching Lin, Hsie-Chia Chang, and Chen-Yi Lee, "A power and area efficient multi-mode FEC processor," IEEE International Symposium on Circuits and Systems (ISCAS), vol. 2, pp. II-253-6. (pdf)

[56] Jhy-Neng Yang, Yi-Chang Cheng, and Chen-Yi Lee, "A design of CMOS broadband amplifier with high-Q active inductor," IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003, pp. 86-89. (pdf)

[55] Hsuan-Yu Liu, Yi-Hsin Yu, Chien-Jen Hung, Terng-Yin Hsu, and Chen-Yi Lee, "Combining adaptive smoothing and decision-directed channel estimation schemes for OFDM WLAN systems," IEEE International Symposium on Circuits and Systems (ISCAS), May 2003, vol. 2, pp. 149-152. (pdf)

[54] Chien-Ching Lin, Chia-Cho Wu, and Chen-Yi Lee, "A low power and high speed Viterbi decoder chip for WLAN applications," European Solid-State Circuits Conference (ESSCIRC), Sept. 2003, pp. 723-726. (pdf)

[53] Wei-Chang Tsai, Chun-Ming Huang, Jiann-Jenn Wang, and Chen-Yi Lee, "Infrastructure for education and research of SOC/IP in Taiwan," IEEE International Conference on Microelectronic Systems Education, 2003, pp. 150-151. (pdf)

[52] Hsie-Chia Chang, Ching-Che Chung, Chien-Ching Lin, and Chen-Yi Lee, "A High Speed Reed-Solomon decoder Chip using Inversionless Decomposed Architecture for Euclidean Algorithm," European Solid-State Circuits Conference (ESSCIRC), Sept. 2002. (pdf)

[51] Keng-Khai Ong, Wei-Hsin Chang, Yi-Chen Tseng, Yew-San Lee, and Chen-Yi Lee, "A high throughput low cost context-based adaptive arithmetic codec for multiple standards," IEEE International Conference on Image Processing (ICIP), 2002, vol. 1, pp. 872-875. (pdf)

[50] Keng-Khai Ong, Yew-San Lee, and Chen-Yi Lee, "Error resilient image coding and smart post-processing error concealment for wireless image transmission," IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), 2002, vol. 4, pp. 4182-4182. (pdf)

[49] Hsie-Chia Chang, Chien-Ching Lin, and Chen-Yi Lee, "A low-power reed-solomon decoder for STM-16 optical communications," IEEE Asia-Pacific Conference on ASIC, 2002, pp. 351-354. (pdf)

[48] Cheng-Hsien Chen and Chen-Yi Lee, "Two-level hierarchical z-buffer for 3D graphics hardware," IEEE International Symposium on Circuits and Systems (ISCAS), 2002, vol. 2, pp. 253-256. (pdf)

[47] Yew-San Lee, Cheng-Mou Yu, Hung-Kuo Wei, Yen-Hsu Shih, and Chen-Yi Lee, "A novel DCT-based bit plane error resilient entropy coding scheme and codec for wireless image communication," IEEE International Symposium on Circuits and Systems (ISCAS), 2002, vol. 5, pp. 121-124. (pdf)

[46] Keng-Khai Ong, Wei-Hsin Chang, Yi-Chen Tseng, Yew-San Lee, and Chen-Yi Lee, "A high throughput context-based adaptive arithmetic codec for JPEG2000," IEEE International Symposium on Circuits and Systems (ISCAS), 2002, vol. 4, pp. 133-136. (pdf)

[45] Ching-Che Chung and Chen-Yi Lee, "An all-digital phase-locked loop for high-speed clock generation," IEEE International Symposium on Circuits and Systems (ISCAS), 2002, vol. 3, pp. 679-682. (pdf)

[44] Tzu-Ming Liu, Bai-Jue Shieh, and Chen-Yi Lee, "An efficient modeling codec architecture for binary shape coding," IEEE International Symposium on Circuits and Systems (ISCAS), 2002, vol. 2, pp. 316-319. (pdf)

[43] Yu-Tsang Chang, Yu-Te Chou, Wei-Chang Tsai, Jiann-Jenn Wang, and Chen-Yi Lee, "FPGA education and research activities in Taiwan," IEEE International Conference on Field-Programmable Technology (FPT), 2002, pp. 445-448. (pdf)

[42] Pao-Lung Chen and Chen-Yi Lee, "A compact software-controlled clock multiplier for SoC application," IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), vol. 1, pp. 499-502. (pdf)

[41] Hung-Kuo Wei, Yew-San Lee, Yen-Hsu Shih, and Chen-Yi Lee, "A novel fixed bit plane error resilient image coding for wireless multimedia transmission," IEEE International Conference on Image Processing (ICIP), 2002, vol. 3, pp. 565-568. (pdf)

[40] Yew-San Lee, Cheng-Mou Yu, and Chen-Yi Lee, "A novel DCT-based bit plane error resilient entropy coding for wireless multimedia communication," IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), 2002, vol. 4, pp. IV-4182. (pdf)

[39] Hsie-Chia Chang and Chen-Yi Lee, "An area-efficient architecture for Reed-Solomon decoder using the inversionless decomposed Euclidean algorithm," IEEE International Symposium on Circuits and Systems (ISCAS), 2001, vol. 2, pp. 649-652. (pdf)

[38] Wei-Hsin Chang, Shuenn-Der Tzeng, and Chen-Yi Lee, "A novel subcircuit extraction algorithm by recursive identification scheme," IEEE International Symposium on Circuits and Systems (ISCAS), 2001, vol. 5, pp. 491-494. (pdf)

[37] Tsai, F.S. and Chen-Yi Lee, "A novel single-bit input all digital synchronizer and demodulator baseband processor for fast frequency hopping system," IEEE International Symposium on Circuits and Systems (ISCAS), 2001, vol. 4, pp. 132-135. (pdf)

[36] Wei-Hsin Chang, Yew-San Lee, Wen-Shiaw Peng, and Chen-Yi Lee, "A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme," IEEE International Symposium on Circuits and Systems (ISCAS), 2001, vol. 4, pp. 330-333. (pdf)

[35] Yew-San Lee, Cheng-Mou Yu, and Chen-Yi Lee, "Error resilient hybrid variable length codec with tough error synchronization for wireless image transmission," IEEE International Symposium on Circuits and Systems (ISCAS), 2001, vol. 4, pp. 326-329. (pdf)

[34] Yi-Chuan Liu, Chung-Cheng Wang, Terng-Yin Hsu, and Chen-Yi Lee, "A wideband digital frequency synthesizer," IEEE International Symposium on Circuits and Systems (ISCAS), 2001, vol. 4, pp. 710-713. (pdf)

[33] Jin-Jer Jong and Chen-Yi Lee, "A novel structure for portable digitally controlled oscillator," IEEE International Symposium on Circuits and Systems (ISCAS), 2001, vol. 1, pp. 272-275. (pdf)

[32] Jhy-Neng Yang, Yi-Chang Cheng, Terng-Yin Hsu, Terng-Ren Hsu, and Chen-Yi Lee, "A 1.75 GHz inductor-less CMOS low noise amplifier with high-Q active inductor load," IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2001, vol. 2, pp. 816-819. (pdf)

[31] Yew-San Lee, Keng-Khai Ong, Wei-Shin Chang, and Chen-Yi Lee, "FORTE-VLC: A Forward Tracing Self-Error Correction Variable Length Code for Image Coding in Wireless Application," European Signal Processing Conference (EUSIPCO), 2000, vol. 2, pp. 1145-1149. (pdf)

[30] Terng-Ren Hsu, Terng-Yin Hsu, Hsuan-Yu Liu, Shuenn-Der Tzeng, Jyh-Neng Yang, and Chen-Yi Lee, "A MLP/BP-based equalizer for NRZ signal recovery in band-limited channels," IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2000, vol. 3, pp. 1340-1342. (pdf)

[29] Hsuan-Yu Liu, Shuenn-Der Tzeng, Yi-Chuan Liu, Chung-Cheng Wang, Temg-Ren Hsu, Temg-Yin Hsu, and Chen-Yi Lee, "A high clock-offset tolerance for DSSS synchronization," IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2000, vol. 2, pp. 944-947. (pdf)

[28] Jyh-Neng Yang, Chen-Yi Lee, Terng-Yin Hsu, Terng-Ren Hsu, and Chung-Cheng Wang, "A 1.5-V, 2.4GHz CMOS low-noise amplifier," IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2000, vol. 2, pp. 1010-1012. (pdf)

[27] Hsie-Chia Chang, Chih-Yu Chen, Shu-Hui Tsai, and Chen-Yi Lee, "A (204,188) Reed-Solomon decoder using decomposed Euclidean algorithm," IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2000, vol. 1, pp. 262-265. (pdf)

[26] Bai-Jue Shieh, Terng-Yin Hsu, and Chen-Yi Lee, "A new approach of group-based VLC codec system," IEEE International Symposium on Circuits and Systems (ISCAS), 2000, vol. 4, pp. 609-612. (pdf)

[25] Yew-San Lee, Cheng-Mou Yu, Wei-Shin Chang, and Chen-Yi-Lee, "HVLC: error correctable hybrid variable length code for image coding in wireless transmission," IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), 2000, vol. 4, pp. 2103-2106. (pdf)

[24] Yew-San Lee, Wei-Shin Chang, Hsin-Han Ho, and Chen-Yi Lee, "Construction of error resilient synchronization codeword for variable-length code in image transmission," IEEE International Conference on Image Processing (ICIP), 2000, pp. 360-363. (pdf)

[23] Yuan-Hau Yeh and Chen-Yi Lee, "A new anti-aliasing algorithm for computer graphics images," IEEE International Conference on Image Processing (ICIP), 1999, vol. 2, pp. 442-446. (pdf)

[22] Wen-Shiaw Peng and Chen-Yi Lee, "An efficient VLSI architecture for separable 2-D discrete wavelet transform," IEEE International Conference on Image Processing (ICIP), 1999, vol. 2, pp. 754-758. (pdf)

[21] Cheng-Hsien Chen and Chen-Yi Lee, "A cost effective lighting processor for 3D graphics application," IEEE International Conference on Image Processing (ICIP), 1999, vol. 2, pp. 792-796. (pdf)

[20] Bai-Jue Shie and Chen-Yi Lee, "An efficient VLC decompression scheme for user-defined coding tables," IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), 1999, vol. 4, pp. 1961-1964. (pdf)

[19] Shin-Chou Juan and Chen-Yi Lee, "Entropy-constrained gradient-match vector quantization for image coding," IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), 1998, vol. 5, pp. 2665-2668. (pdf)

[18] Bai-Jue Shieh, Yew-San Lee, and Chen-Yi Lee, "A high throughput variable length decoder with modified memory based architecture," IEEE International Symposium on Circuits and Systems (ISCAS), 1998, vol. 2, pp. 486-489. (pdf)

[17] Bor-Cheng Shih, Yen-Hou Yeh, and Chen-Yi Lee, "An Area Efficient Architecture For 3d Graphics Shading *," IEEE International Conference on Consumer Electronics (ICCE), 1998, pp. 462-464. (pdf)

[16] Terng-Yin Hsu and Chen-Yi Lee, "Effects of shadowing, multipath fading, antenna diversity in DS/CDMA for cellular mobile radio with reverse-link power control," IEEE Global Telecommunications Conference (GLOBECOM), 1997, vol. 2, pp. 894-898. (pdf)

[15] Yuan-Hau Yeh and Chen-Yi Lee, "Buffer size optimization for full-search block matching algorithms," IEEE International Conference on Application-Specific Systems, Architectures and Processors, 1997, pp. 76-85. (pdf)

[14] Yew-San Lee, Jin-Jer-Jong, Tsyr-Shiou Perng, Li-Chyun Hsu, Ming-Yang Jaw, and Chen-Yi Lee, "A memory-based architecture for very-high-throughput variable length codec design," IEEE International Symposium on Circuits and Systems (ISCAS), 1997, vol. 3, pp. 2096-2099. (pdf)

[13] Jer-Min Tsai, Hsin-Hsiung Fang, Chi-Cheng Ju, and Chen-Yi Lee, "A multicasting solution for ATM video applications," IEEE International Symposium on Circuits and Systems (ISCAS), 1997, vol. 4, pp. 2781-2784. (pdf)

[12] Chen-Yi Lee, "A cost-effective VLSI architecture for high-throughput sequential decoder," IEEE International Symposium on Circuits and Systems (ISCAS), 1996, vol. 4, pp. 328-331. (pdf)

[11] Terng-Yin Hsu and Chen-Yi Lee, "The outage probability in DS/CDMA for cellular mobile radio with imperfect power control," IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC), 1996, vol. 1, pp. 183-187. (pdf)

[10] Yuan-Hau Yeh and Chen-Yi Lee, "Scalable VLSI architectures for full-search block matching algorithms," IEEE International Conference on Image Processing (ICIP), 1996, vol. 1, pp. 1035-1038. (pdf)

[9] Mei-Cheng Lu and Chen-Yi Lee, "Semi-systolic array based motion estimation processor design," IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), 1995, vol. 5, pp. 3299-3302. (pdf)

[8] E.G. Tzeng and Chen-Yi Lee, "An efficient memory architecture for motion estimation processor design," IEEE International Symposium on Circuits and Systems (ISCAS), 1995, vol. 1, pp. 712-715. (pdf)

[7] Ren-Yang Yang and Chen-Yi Lee, "High-throughput data compressor designs using content addressable memory," IEEE International Symposium on Circuits and Systems (ISCAS), 1994, vol. 4, pp. 147-150. (pdf)

[6] Shih-Chou Juan, Yen-Jean Chao, and Chen-Yi Lee, "Finite state vector quantization with multi-path tree search strategy for image/video coding," IEEE International Symposium on Circuits and Systems (ISCAS), 1994, vol. 3, pp. 181-184. (pdf)

[5] Wen-Wei Yang, Li-Fu Jeng, and Chen-Yi Lee, "Design of a fast sequential decoding algorithm based on dynamic searching strategy," IEEE International Symposium on Circuits and Systems (ISCAS), 1994, vol. 3, pp. 165-168. (pdf)

[4] Chen-Yi Lee, Shih-Chou Juan, and Wen-Wei Yang, "An Area-efficient Maximum/mininium Detection Circuit For Digital And Video Signal Processing," IEEE International Symposium on Circuits and Systems (ISCAS), 1993, pp. 223-226. (pdf)

[3] Po-Wen Hsieh, Jer-Min Tsai, and Chen-Yi Lee, "An Area-efficient Median Filtering IC For Image/video Applications," IEEE International Conference on Consumer Electronics (ICCE), 1993, pp. 260-261. (pdf)

[2] Chen-Yi Lee and Ching-Chung Yen, "Probability, estimation In An Arithmetic Codee For Model-based Image Coding," IEEE International Workshop on Intelligent Signal Processing and Communication Systems (ISPACS), 1992, pp. 200-210. (pdf)

[1] Chen-Yi Lee and Shin-Chou Juan, "An ASIC architecture for real-time image/video coding based on fixed-basis-distortion vector quantization," IEEE International Symposium on Circuits and Systems (ISCAS), 1992, vol. 4, pp. 1676-1679. (pdf)