[85] Eugene Lee and Chen-Yi Lee, "PPG-Based Smart Wearable Device with Energy-Efficient Computing for Mobile Health-care Applications," IEEE Sensors Journal,vol. 21, no. 12, pp. 13564-13573 (2021)

[84] Chun-Chi Chen, Yun-Sheng Chan, Yu-Hao Fang, Yun-Ming Wang, and Chen-Yi Lee, "Rapid Portable Electrical Biosensing Design with Dielectrophoresis and its Applications for Cardiac Biomarker Detection," IEEE Sensors Journal,Vol. 20, No. 16, pp. 8981-8989 (2020)

[83] Yingchieh Ho, Shu-Yu Hsu, Chen-Yi Lee, "A Variation-Tolerant Subthreshold to Superthreshold Level Shifter for Heterogeneous Interfaces," IEEE Trans. on Circuits and Systems 63-II(2): 161-165 (2016)

[82] Chia-Lung Lin, Shu-Wen Tu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee "An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm," IEEE Trans. on Circuits and Systems 63-II(9): 863-867 (2016)

[81] Chia-Lung Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, "Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture," IEEE Trans. on Circuits and Systems 62-I(10): 2523-2532 (2015)

[80] Chang-Hung Tsai, Yu-Ting Chih, Wing Hung Wong, Chen-Yi Lee, "A Hardware-Efficient Sigmoid Function With Adjustable Precision for a Neural Network System," IEEE Trans. on Circuits and Systems 62-II(11): 1073-1077 (2015)

[79] Szu-Chi Chung, Jing-Yu Wu, Hsing-Ping Fu, Jen-Wei Lee, Hsie-Chia Chang, Chen-Yi Lee,"Efficient Hardware Architecture of ηT Pairing Accelerator Over Characteristic Three," IEEE Trans. VLSI Syst. 23(1): 88-97 (2015)

[78] Chi-Heng Yang, Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee, "An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability," IEEE Trans. VLSI Syst. 23(7): 1235-1244 (2015)

[77] Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, "A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications.," IEEE Trans. on Circuits and Systems 62-I(2): 507-516 (2015)

[76] X. R. Lee, C. W. Yang, C. L. Chen, H. C. Chang, and C. Y. Lee, "An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 3, Mar. 2015, pp. 301-305 (pdf)

[75] Chen-Yi Lee, Kelvin Yi-Tse Lai, and Shu-Yu Hsu, "A Sensor-Fusion Solution for Mobile Health-Care Applications," in Smart Sensor Systems (invited), Springer Press, accepted and to appear.

[74] Kelvin Yi-Tse Lai, Yu-Tao Yang, and Chen-Yi Lee, "An Intelligent Digital Microfluidics Processor for Biomedical Applications," Journal of Signal Processing Systems (JSPS) (invited), E-First version, Aug. 2014.

[73] Xin-Ru Lee, Chih-Lung Chen, H. C. Chang, and Chen-Yi Lee, "A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications," has been accepted by IEEE Transaction on Circuits and Systems I: Regular Papers. (pdf)

[72] Yi-Min Lin, Chih-Hsiang Hsu, Hsie-Chia Chang, and Chen-Yi Lee, "A 2.56 Gb/s Soft RS (255, 239) Decoder Chip for Optical Communication Systems," IEEE Transactions on Circuits and Systems-I (TCAS-I), Vol. 61, no. 7, July 2014, pp. 2110-2118, Nov. 2013. (pdf)

[71] Shu-Yu Hsu, Yingchieh Ho, Po-Yao Chang, Chauchin Su, and Chen-Yi Lee, "A 48.6-to-105.2μW Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications," IEEE Journal of Solid-State Circuits, Accepted.

[70] Gary Wang, Daniel Teng, Yi-Tse Lai, Yi-Wen Lu, Yingchieh Ho, and Chen-Yi Lee, "Field-Programmable Lab-On-a-Chip Based on MEDA Architecture," IET Nanobiotechnology, E-First version, Oct. 21, 2013, July. 2012.

[69] Jen-Wei Lee, Hsie-Chia Chang, and Chen-Yi Lee, "An Efficient Power-Analysis-Resistant DF-ECC Processor Using Heterogeneous Dual-PE Architecture," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 22, no. 1, Jan. 2014, pp. 49-61, Dec. 2012.

[68] Yi-Min Lin, Hsie-Chia Chang, and Chen-Yi Lee, "Improved High Code-Rate Soft BCH Decoder Architectures with One Extra Error Compensation," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 21, no. 11, Nov. 2013, pp. 2160-2164, Oct. 2012. (pdf)

[67] Wei-Hao Sung, Ching-Che Chung, and Chen-Yi Lee, "An Ultra-Low Voltage Implicit Multiplexed Differential Flip-Flop with Enhanced Noise Immunity," Electronics Letters, Vol. 48, Issue 23, Nov. 8, 2012, PP. 1452-1454, Oct. 2012.

[66] Chien-Ying Yu, Ching-Che Chung, Chia-Jung Yu, and Chen-Yi Lee, "A Low-Power DCO using Interlaced Hysteresis Delay Cells," IEEE Transactions on Circuits and Systems-II (TCAS-II), Vol. 59, no. 10, Oct. 2012, pp. 673-677, July 2012.

[65] Jen-Wei Lee, Ju-Hung Hsiao, Hsie-Chia Chang, and Chen-Yi Lee, "An Efficient DPA Countermeasure with Randomized Montgomery Operations for DF-ECC Processor," IEEE Transactions on Circuits and Systems-II (TCAS-II), Vol. 59, no. 5, May 2012, pp. 287-291, Feb. 2012.

[64] Po-Chun Liu, Hsie-Chia Chang, and Chen-Yi Lee, "A True Random-Based Differential Power Analysis Countermeasure Circuit for an AES Engine," IEEE Transactions on Circuits and Systems-II (TCAS-II), Vol. 59, no. 2, Feb. 2012, pp. 103-107, Feb 2012. (pdf)

[63] Chien-Ying Yu, Jui-Yuan Yu, and Chen-Yi Lee, "A Low Voltage All-Digital On-Chip Oscillator Using Relative Reference Modeling," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 20, No. 9, Sep. 2012, pp. 1615-1620, July 2012.

[62] Tsan-Wen Chen, Ping-Yuan Tsai, Jui-Yuan Yu, and Chen-Yi Lee, "A Sub-mW All-Digital Signal Component Separator with Branch Mismatch Compensation for OFDM LINC Transmitters," IEEE Journal of Solid-State Circuits (JSSC), Vol. 46, No. 11, Nov. 2011, pp. 2514-2523, July 2012.

[61] Yi-Min Lin, Chi-Heng Yang, Chih-Hsiang Hsu, Hsie-Chia Chang, and Chen-Yi Lee, "A MPCN-Based Parallel Architecture in BCH Decoders for NAND Flash Memories", IEEE Transactions on Circuits and Systems-II (TCAS-II), Vol. 58, no. 10, Oct. 2011, pp. 682-686, July 2012. (pdf)

[60] Wei-Hao Sung, Jui-Yuan Yu, and Chen-Yi Lee, "A Robust Frequency Tracking Loop for Energy-Efficient Crystal-Less WBAN Systems", IEEE Transactions on Circuits and Systems-II (TCAS-II), Vol. 58, no. 10, Oct. 2011, pp. 637-641, July 2012.

[59] Ching-Che Chung, Jui-Yuan Yu, Shiou-Ru Jang, and Chen-Yi Lee, "A 90nm All-digital Smart Temperature Sensor with Wireless Body Area Network Baseband Transceiver for Biotelemetry Applications", Journal of Signal Processing Systems, Vol. 42, no. 2, Aug. 2011, pp. 241-248, July 2012.

[58] Chien-Chen Lin, Yao Li, Chen-Yi Lee, "A Predefined Bit-Plane Comparison Coding for Mobile Video Applications," IEEE Transactions on Circuits and Systems-II (TCAS-II): Express Briefs, vol. 58, no.7, pp. 437-441, July 2011. (pdf)

[57] Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, and Chen-Yi Lee, "An Efficient Power-Analysis-Resistant DF-ECC Processor Using Heterogeneous Dual-PE Architecture," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 22, no. 1, pp. 49-61, Dec. 2012.

[56] Jen-Wei Lee, Ju-Hung Hsiao, Hsie-Chia Chang, and Chen-Yi Lee, "An Efficient DPA Countermeasure with Randomized Montgomery Operations for DF-ECC Processor," IEEE Transactions on Circuits and Systems-II (TCAS-II): Express Briefs, vol. 59, no. 5, pp. 287-291, May. 2012. (pdf)

[55] Chih-Lung Chen, Yu-Hsiang Lin, Hsie-Chia Chang, and Chen-Yi Lee, "A 2.37Gb/s 284.8mW Rate-Compatible (491,3,6) LDPC-CC Decoder," IEEE Journal of Solid-State Circuits (JSSC), vol. 47, no. 4, pp. 817-831, 2012. (pdf)

[54] Yi-Min Lin, Hsie-Chia Chang, and Chen-Yi Lee, "A MPCN-Based Parallel Architecture in BCH Decoders for NAND Flash Memory Devices," IEEE Transactions on Circuits and Systems-II (TCAS-II), vol. 58, no. 10, pp. 682-686, Oct. 2011. (pdf)

[53] Wei-Hao Sung, Jui-Yuan Yu, and Chen-Yi Lee, "A Robust Frequency Tracking Loop for Energy-Efficient Crystalless WBAN Systems," IEEE Transactions on Circuits and Systems-II (TCAS-II), vol. 58, no. 10, 2011. (pdf)

[52] Chien-Ying Yu, Jui-Yuan Yu and Chen-Yi Lee, "A Low Voltage All-Digital On-Chip Oscillator Using Relative Reference Modeling," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 20, no. 9, pp. 1615-1620, Sept. 2012. (pdf)

[51] Tsan-Wen Chen, Ping-Yuan Tsai, Jui-Yuan Yu, and Chen-Yi Lee, "A Sub-mW All-Digital Signal Component Separator with Branch Mismatch Compensation for LINC Transmitters," IEEE Journal of Solid-State Circuits (JSSC), vol. 46, no. 11, pp. 2514-2523, Nov. 2011. (pdf)

[50] Ching-Che Chung, Jui-Yuan Yu, Shiou-Ru Jang, and Chen-Yi Lee, "A 90nm All-digital Smart Temperature Sensor with Wireless Body Area Network Baseband Transceiver for Biotelemetry Applications," Journal of Signal Processing Systems, vol. 46, no. 2, pp. 241-248, Aug. 2011. (pdf)

[49] Shu-Yu Hsu, Jui-Yuan Yu, and Chen-Yi Lee, "A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications," IEEE Transactions on Circuits and Systems-II (TCAS-II), vol. 57, no. 12, pp. 951-955, Dec. 2010. (pdf)

[48] Yi-Min Lin, Chih-Lung Chen, Hsie-Chia Chang, and Chen-Yi Lee, "A 26.9 K 314.5 Mb/s Soft (32400,32208) BCH Decoder Chip for DVB-S2 System," IEEE Journal of Solid-State Circuits (JSSC), vol. 45, no. 11, pp. 2330-2340, 2010. (pdf)

[47] Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, "Fast-Lock All-Digital DLL and Digitally-Controlled Phase Shifter for DDR Controller Applications," IEICE Electronics Express, vol. 7, no. 9, pp. 634-639, May 2010. (pdf)

[46] Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, "Wide duty cycle range synchronous mirror delay designs," IET Electronics Letters, vol. 46, no. 5, pp. 338-340, Mar 2010. (pdf)

[45] Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, "A Low-Power and Portable Spread Spectrum Clock Generator for SoC Applications," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 19, no. 6, pp. 1113-1117, Jun. 2011. (pdf)

[44] Po-Chun Liu, Hsie-Chia Chang, and Chen-Yi Lee, "A Low Overhead DPA Countermeasure Circuit Based on Ring Oscillators," IEEE Transactions on Circuits and Systems-II (TCAS-II), vol. 57, no. 7, pp. 546-550, 2010. (pdf)

[43] Cheng-Chi Wong, Ming-Wei Lai, Chien-Ching Lin, Hsie-Chia Chang, and Chen-Yi Lee, "Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture," IEEE Journal of Solid-State Circuits (JSSC), vol. 45, no. 2, pp. 422-432, 2010. (pdf)

[42] Chen-Fong Hsiao, Yuan Chen, and Chen-Yi Lee, "A Generalized Mixed-Radix Algorithm for Memory-Based FFT Processors," IEEE Transactions on Circuits and Systems-II (TCAS-II), vol.57, no.1, pp. 26-30, 2010. (pdf)

[41] Chih-Hao Liu, Chien-Ching Lin, Shau-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu and Shyh-Jye Jou, "Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network," IEEE Transactions on Circuits and Systems-II (TCAS-II), vol.56, no.9, pp.734-738, Sep. 2009. (pdf)

[40] Hsie-Chia Chang, Chien-Ching Lin, Fu-Ku Chang, and Chen-Yi Lee, "A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders," IEEE Transactions on Circuits and Systems-I (TCAS-I): Regular Papers, vol.56, no.9, pp. 1960-1967, Sep. 2009. (pdf)

[39] Tsan-Wen Chen, Jui-Yuan Yu, Chien-Ying Yu, and Chen-Yi Lee, "A 0.5 V 4.85 Mbps Dual-Mode Baseband Transceiver With Extended Frequency Calibration for Biotelemetry Applications," IEEE Journal of Solid-State Circuits (JSSC), vol. 44, pp. 2966-2976, Nov. 2009. (pdf)

[38] Jui-Yuan Yu, Ching-Che Chung, and Chen-Yi Lee, "A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems," IEEE Transactions on Circuits and Systems-II (TCAS-II): Express Briefs, vol. 55, no. 9, Sep. 2008. (pdf)

[37] Chih-Hao Liu, Shau-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, and Shyh-Jye Jou, "An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications," IEEE Journal of Solid-State Circuits (JSSC), vol. 43, pp. 684-694, Mar. 2008. (pdf)

[36] Yuan Chen, Yu-Wei Lin, Yu-Chi Tsao, and Chen-Yi Lee, "A 2.4-Gsample/s DVFS FFT processor for MIMO OFDM communication systems," IEEE Journal of Solid-State Circuits (JSSC), vol. 43, pp. 1260-1273, May 2008. (pdf)

[35] Yuan Chen, Yu-Chi Tsao, Yu-Wei Lin, Chin-Hung Lin, and Chen-Yi Lee, "An indexed-scaling pipelined FFT processor for OFDM-based WPAN applications," IEEE Transactions on Circuits and Systems-II (TCAS-II): Express Briefs, vol. 55, no. 2, pp. 146-150, Feb. 2008. (pdf)

[34] Duo Sheng, Ching Che Chung, and Chen Yi Lee, "An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications," IEEE Transactions on Circuits and Systems-II (TCAS-II): Express Briefs, Exp. Briefs, vol. 54, no. 11, pp. 954-958, Nov. 2007. (pdf)

[33] Yu-Wei Lin and Chen-Yi Lee, "Design of an FFT/IFFT Processor for MIMO OFDM Systems," IEEE Transactions on Circuits and Systems-I (TCAS-I): Regular Papers, vol. 54, no. 4, Apr. 2007. (pdf)

[32] Tsu-Ming Liu, Ting-An Lin, Sheng-Zen Wang, Wen-Ping Lee, Jiun-Yan Yang, Kang-Cheng Hou, and Chen-Yi Lee, "A 125 micro-W, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications," IEEE Journal of Solid-State Circuits (JSSC), vol. 42, no. 1, Jan. 2007. (pdf)

[31] TSU-MING LIU AND CHEN-YI LEE, "Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead," Journal of VLSI Signal Processing, 2007. (pdf)

[30] Tsu-Ming Liu, Sheng-Zen Wang, Bai-Jue Shieh, and Chen-Yi Lee, "A New Soft Variable Length Decoder for Wireless Video Transmission," IEEE Transactions on Circuits and Systems for Video Technology (T-CSVT), vol. 17, no. 2, Feb. 2007. (pdf)

[29] Tsu-Ming Liu, Wen-Ping Lee, and Chen-Yi Lee, "An In/Post-Loop Deblocking Filter With Hybrid Filtering Schedule," IEEE Transactions on Circuits and Systems for Video Technology (T-CSVT), vol. 17, no. 7, Jul. 2007. (pdf)

[28] Lei-Fone Chen and Chen-Yi Lee, "Design of a DVB-T/H COFDM Receiver for Portable Video Applications," IEEE Communications Magazine, Aug. 2007. (pdf)

[27] Pao-Lung Chen, Ching-Che Chung, Jyh-Neng Yang, and Chen-Yi Lee, "A Clock Generator With Cascaded Dynamic Frequency Counting Loops for Wide Multiplication Range Applications," IEEE Journal of Solid-State Circuits (JSSC), vol. 41, no. 6, Jun. 2006. (pdf)

[26] Wen-Hsiao Peng, Tihao Chiang, Hsueh-Ming Hang, and Chen-Yi Lee, "A Context Adaptive Bit-Plane Coder With Maximum-Likelihood-Based Stochastic Bit-Reshuffling Technique for Scalable Video Coding," IEEE Transactions on Multimedia, vol. 8, no. 4, Aug. 2006. (pdf)

[25] Tsu-Ming Liu, Ting-An Lin, Sheng-Zen Wang, and Chen-Yi Lee, "A Low-Power Dual-Mode Video Decoder for Mobile Applications," IEEE Communications Magazine, Aug. 2006. (pdf)

[24] Hsuan-Yu Liu, and Chen-Yi Lee, "A Low-Complexity Synchronizer for OFDM-Based UWB System," IEEE Transactions on Circuits and Systems-II (TCAS-II): Express Briefs, vol. 53, no. 11, Nov. 2006. (pdf)

[23] Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, and Chen-Yi Lee, "A Low Power Turbo/Viterbi Decoder for 3GPP2 Applications," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 14, no. 4, Apr. 2006. (pdf)

[22] Yu-Wei Lin, Hsuan-Yu Liu, and Chen-Yi Lee, "A 1-GS/s FFT/IFFT Processor for UWB Applications," IEEE Journal of Solid-State Circuits (JSSC), vol. 40, no. 8, Aug. 2005. (pdf)

[21] Pao-Lung Chen, Ching-Che Chung, and Chen-Yi Lee, "A Portable Digitally Controlled Oscillator Using Novel Varactors," IEEE Transactions on Circuits and Systems-II (TCAS-II): Express Briefs, vol. 52, no. 5, May 2005. (pdf)

[20] Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, and Chen-Yi Lee, "Design of a Power-Reduction Viterbi Decoder for WLAN Applications," IEEE Transactions on Circuits and Systems-I (TCAS-I): Regular Papers, vol. 52, no. 6, Jun. 2005. (pdf)

[19] Yu-Wei Lin, Hsuan-Yu Liu, and Chen-Yi Lee, "A Dynamic Scaling FFT Processor for DVB-T Applications," IEEE Journal of Solid-State Circuits (JSSC), vol. 39, no. 11, Nov. 2004. (pdf)

[18] Ching-Che Chung and Chen-Yi Lee, "A New DLL-Based Approach for All-Digital Multiphase Clock Generation," IEEE Journal of Solid-State Circuits (JSSC), vol. 39, no. 3, Mar. 2004. (pdf)

[17] Hsie-Chia Chang, Chien-Ching Lin, and Chen-Yi Lee, "A low-power design for the Reed-Solomon decoder," Journal of Circuits, Systems, and Computers (JCSC), vol. 12, no. 2, pp. 159-170, Apr. 2003. (pdf)

[16] Ching-Che Chung, and Chen-Yi Lee, "An All-Digital Phase-Locked Loop for High-Speed Clock Generation," IEEE Journal of Solid-State Circuits (JSSC), vol. 38, no. 2, Feb. 2003. (pdf)

[15] Cheng-Hsien Chen, Chen-Yi Lee, "Two-level hierarchical Z-buffer with compression technique for 3D graphics hardware," Visual Computer, 2003. (pdf)

[14] Yew-San Lee, Keng-Khai Ong, and Chen-Yi Lee, "Error-Resilient Image Coding (ERIC) With Smart-IDCT Error Concealment Technique for Wireless Multimedia Transmission," IEEE Transactions on Circuits and Systems for Video Technology (T-CSVT), vol. 13, no. 2, Feb. 2003. (pdf)

[13] Terng-Yin Hsu, Terng-Ren Hsu, Chung-Cheng Wang, Yi-Chuan Liu, and Chen-Yi Lee, "Design of a Wide-Band Frequency Synthesizer Based on TDC and DVC Techniques," IEEE Journal of Solid-State Circuits (JSSC), vol. 37, no. 10, Oct. 2002. (pdf)

[12] Bai-Jue Shieh, Yew-San Lee, and Chen-Yi Lee, "A New Approach of Group-Based VLC Codec System with Full Table Programmability," IEEE Transactions on Circuits and Systems for Video Technology (T-CSVT), vol. 11, no. 2, Feb. 2001. (pdf)

[11] Hsie-Chia Chang, C. Bernard Shung, and Chen-Yi Lee, "A Reed¡VSolomon Product-Code (RS-PC) Decoder Chip for DVD Applications," IEEE Journal of Solid-State Circuits (JSSC), vol. 36, no. 2, Feb. 2001. (pdf)

[10] Terng-Yin Hsu, Chung-Cheng Wang, and Chen-Yi Lee, "Design and Analysis of a Portable High-Speed Clock Generator," IEEE Transactions on Circuits and Systems-II (TCAS-II): Analog and Digital Signal Processing, vol. 48, no. 4, Apr. 2001. (pdf)

[9] Bai-Jue Shieh, Yew-San Lee, and Chen-Yi Lee, "A High-Throughput Memory-Based VLC Decoder with Codeword Boundary Prediction," IEEE Transactions on Circuits and Systems for Video Technology (T-CSVT), vol. 10, no. 8, Dec. 2000. (pdf)

[8] Terng-Yin Hsu, Bai-Jue Shieh, and Chen-Yi Lee, "An All-Digital Phase-Locked Loop (ADPLL)-Based Clock Recovery Circuit," IEEE Journal of Solid-State Circuits (JSSC), vol. 34, no. 8, Aug. 1999. (pdf)

[7] Yuan-Hau Yeh and Chen-Yi Lee, "Cost-Effective VLSI Architectures and Buffer Size Optimization for Full-Search Block Matching Algorithms," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 7, no. 3, Sept. 1999. (pdf)

[6] Yew-San Lee, Bai-Jue Shieh, and Chen-Yi Lee, "A Generalized Prediction Method for Modified Memory-Based High Throughput VLC Decoder Design," IEEE Transactions on Circuits and Systems-II (TCAS-II): Analog and Digital Signal Processing, vol. 46, no. 6, Jun. 1999. (pdf)

[5] CHEN-YI LEE AND MEI-CHENG LU, "An Efficient VLSI Architecture for Full-Search Block Matching Algorithms," Journal of VLSI Signal Processing, vol. 15, pp. 275-282, 1997. (pdf)

[4] Jer-Min Tsai, Hsin-Hsiung Fang, and Chen-Yi Lee, "A Multicasting Solution for ATM Video Applications," IEEE Transactions on Circuits and Systems for Video Technology (T-CSVT), vol. 7, no. 4, Aug. 1997. (pdf)

[3] Chen-Yi Lee, Shih-Chou Juan, and Yen-Juan Chao, "Finite State Vector Quantization with Multipath Tree Search Strategy for ImageNideo Coding," IEEE Transactions on Circuits and Systems for Video Technology (T-CSVT), vol. 6, no. 3, Jun. 1996. (pdf)

[2] Chen-Yi Lee, Shih-Chou Juan and Wen-Wei Yang, "A Parallel Bit-Level Maximum/Minimum Selector for Digital and Video Signal Processing," IEEE Transactions on Circuits and Systems-II (TCAS-II): Analog and Digital Signal Processing, vol. 41, no. 41, Oct. 1994. (pdf)

[1] Chen-Yi Lee, Po-Wen Hsieh, and Jer-Min Tsai, "High-speed Median Filter Designs Using Shiftable Content-Addressable Memory," IEEE Transactions on Circuits and Systems for Video Technology (T-CSVT), vol. 4, no. 6, Dec. 1994. (pdf)